module axi_dig_disp_dev (
	output [8-1:0] 		seg,
	output [4-1:0] 		dig,
    Axi4LiteIf.slave    slave
);

	axi_eight_digit_7_seg_display_v1_0_S00_AXI # ( 
		.C_S_AXI_DATA_WIDTH(32),
		.C_S_AXI_ADDR_WIDTH(4)
	) axi_eight_digit_7_seg_display_v1_0_S00_AXI_inst (
		.seg(seg),
		.dig(dig),
		.S_AXI_ACLK		(slave.clk),
		.S_AXI_ARESETN	(slave.rst_n),
		.S_AXI_AWADDR	(slave.awaddr),
		.S_AXI_AWPROT	(slave.awprot),
		.S_AXI_AWVALID	(slave.awvalid),
		.S_AXI_AWREADY	(slave.awready),
		.S_AXI_WDATA	(slave.wdata),
		.S_AXI_WSTRB	(slave.wstrb),
		.S_AXI_WVALID	(slave.wvalid),
		.S_AXI_WREADY	(slave.wready),
		.S_AXI_BRESP	(slave.bresp),
		.S_AXI_BVALID	(slave.bvalid),
		.S_AXI_BREADY	(slave.bready),
		.S_AXI_ARADDR	(slave.araddr),
		.S_AXI_ARPROT	(slave.arprot),
		.S_AXI_ARVALID	(slave.arvalid),
		.S_AXI_ARREADY	(slave.arready),
		.S_AXI_RDATA	(slave.rdata),
		.S_AXI_RRESP	(slave.rresp),
		.S_AXI_RVALID	(slave.rvalid),
		.S_AXI_RREADY	(slave.rready)
	);



endmodule
